MOV
- 操作数不能都是memory
- register must match the suffix
- movq 的立即数必须再32bit补码能表示的范围内，然后该立即数被符号扩展
- movabsq可以有任意的64bit立即数（没有明确指出是否是补码），但是destination必须是register
- movz、movs系列have a register or memory location as the source and a register as the destination.
- cltq: SignExtend(%eax) -> %rax
- movzlq不存在，可以用movl实现。但是movzbq、movzwq为什么存在，不是可以用movzbl、movzwl实现（practice problem3.4第四题）。同样的，sal、shl为什么同时存在
其他指令
- leaq:
- has no other size variants
- The destination operand must be a register.
- Unary Operations:
- operand can be either a register or a memory location.
- Binary Operations:
- the second operand is used as both a source and a destination
- the first operand can be either an immediate value, a register, or a memory location. The second can be either a register or a memory location.
- the two operands can’t both be memory location
- when the second operand is a memory location, the processor must read the value from memory, perform the operation, and then write the result back to memory.
- Shift Operations
- shift amount is given first and the value to shift is given second. 因为第二个操作数是register或者memory location，所以不能用立即数作为the value to shift
- shift amount can be imm value or %cl
- a shift instruction operating on data values that are w bits long determines the shift amount from the low-order m bits of register %cl, where $2^m=w$. The higher-order bits are ignored.For example, when register %cl has hexadecimal value 0xFF, then instruction salb would shift by 7, while salw would shift by 15, sall would shift by 31, and salq would shift 63
- destination can be register or memory location
浮点指令
- vmovss, vmovd的操作数可以是（第一个source，第二个destination）
- memory， XMM
- XMM， memory
- 按照书上的描述，好像还可以XMM， XMM
- vmovaps, vmovapd可以从XMM to XMM，读写内存时，地址需要16字节对齐。
- vcvttss2si,, vcvttss2siq的destination都是通用寄存器（非XMM）
- vcvtsi2ss, vcvtsi2sd, vcvtsi2ssq, vcvtsi2sdq的destination都是XMM，第二个source操作数都是XMM（可能只是书上讲的情形有这个要求而已）
- vunpcklps, vcvtps2pd：single to double（其实是有vcvtsd2ss）
- vmovddup, vcvtpd2psx：double to single（其实是有vcvtsi2sdq）
- vaddss, vsubss, vmulss, vdivss, vmaxss, vminss, sqrtss第一个source是XMM或者memory，第二个source和destination必须是XMM
- vaddsd, vsubsd, vmulsd, vdivsd, vmaxsd, vminsd, sqrtsd同样
MISC
- intel format have reverse order operands;
- Different instructions allow different ranges of immediate values; the assembler will automatically select the most compact way of encoding a value
- Such a reference has four components: an immediate offset Imm, a base register rb, an index register ri, and a scale factor s, where s must be 1, 2, 4, or 8. Both the base and index must be 64-bit registers.
- Any instruction that generates a 32-bit value for a register also sets thehigh-order portion of the register to 0
- 后缀的匹配